The present invention relates to a DC-to-DC converter provided with means for optimizing power consumption as the load level varies.
In static converters operating in a switching mode, conversion efficiency may be improved by reducing the conduction losses of the switch, given by the product between the internal resistance of the switching device and the current, plus the switching losses that are a function of the frequency and speed of the transitions. Normally a converter is designed for a certain level of switched current under normal steady state conditions of operation, by establishing on a case by case basis, the size of the power devices and the switching frequency and duty-cycle when operating in a steady state condition. Generally, for relatively high switched currents, conduction losses will be more relevant, while for relatively low switched currents, i.e., during periods of operation when the current level and duty-cycle of the converter are reduced, switching losses become more and more relevant.
Several techniques are known for reducing the switching frequency of the power switch when the load level decreases in order to increase the overall conversion efficiency of the system. The known solutions may be classified in two distinct categories:
a) The control circuit of the converter is completely switched-off with the exception of the circuits that handle the turn-off phase. The control circuit is reactivated when the output voltage drops below a preset minimum threshold and switched off again when the output voltage becomes higher than a preset maximum threshold. PA1 b) The control system of the switch is maintained always active, but the switch is commanded to switch for brief bursts of high frequency pulses (burst mode). The duration of these bursts is established by the time necessary for the output voltage, once it has dropped below a minimum threshold, to rise back again above a maximum threshold.
Known approaches of the first category have the drawback that in case of integrated buck converters, where the power switch transistor may also be integrated, it is necessary to keep active the circuit that directly control the turn-on and the turn-off of the power transistor. This means that the limited saving that can be achieved may be negatively counterbalanced by an increased complexity of the circuit because special monitoring circuits of internal voltages must be introduced.
The approaches of the second category, though better adapted to situations where a solution of the first category is not useable, are still not very effective in terms of power saving. This is due to the fact that during periods of operation at a relatively low load level of the converter, switching losses persist during burst periods.
Therefore there is a need for a converter that would allow an optimization of its efficiency during periods of operation when the converter outputs a relatively low current, i.e., during periods of operation at a relatively low load level.
This objective is fully met by the converter of the present invention which is characterized by the ability to drive the power switch with a signal produced by a conventional PWM control network during operation at a relatively high load level and conversely with a signal produced by a hysteresis comparator, during operation at a relatively low load level.
The automatic selection of one or the other mode of operation of the converter is effected by logic circuitry capable of generating an enable/disable signal for the mutually exclusive control networks.
Monitoring of the load level of the converter is effected without employing dissipative sensing devices, but by comparing the duty-cycle of either one or the other of the two alternate driving signals with a reference value. In the case of the driving signal produced by the PWM control network, which is active during normal conditions of operation with a relatively high load of the converter, its current duty-cycle is compared with a signal representing a preset reference, or threshold, duty-cycle, which may be set between 30% and 50% of the designed steady state duty-cycle under normal operating condition of the converter.
In practice, the converter automatically passes from a "continuous" mode of operation, controlled by a conventional PWM control network, to a "discontinuous" mode of operation during which the turning-on and the turning-off of the power switch are controlled directly as a function of the output voltage in a hysteretic mode, without pulses synchronous with the clock signal of the circuit, or conversely, in dependence on the load level. This almost entirely eliminates the switching losses during operation of the converter at a low load level.